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    Quick Facts

    Total Fees
    1.24 L
    Exam
    GATE
    Seats
    30

    Fees Details

    General

    1.24 L

    Disclaimer: Data for total fees has been calculated based on all years/semesters as provided by the college. The actual fees may vary.

    Course Details

    MODE

    Full time

    DURATION

    24 Months

    Master of Engineering (ME) in VLSI Design is a two-year full-time postgraduate program recognized by AICTE and offered by the Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal.


    Important dates

    Exams and EventsDates
    GATE
    Answer Key Date - Final answer key (Mode - Online)
    22 Aug'26 - 18 Sep'26
    GATE
    Score Card Date (Mode - Online)
    26 Sep'26 - 26 Sep'26
    GATE
    Result Date (Mode - Online)
    18 Oct'26 - 18 Oct'26

    Eligibility Criteria

    A candidate seeking admission to M.E./M.Tech. courses should be a Graduate in Engg./Technology with at least 50% marks in aggregate, Candidate belonging to SC, ST, OBC(Excluding Creamy Layer) category of Madhya Pradesh with at least 45% marks in aggregate. Bachelors degree be of minimum of four years duration should have been obtained from any AICTE approved institution or Indian University or from a foreign University recognised by AIU or any Institutes of national importance (i.e. IITs/IISc/ NITs etc.), duly recognized by the MHRD, as equivalent thereto.

    Admission Details

    Through GATE entrance.

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