Total Fees 1.24 L | Exam GATE | Seats 30 |
₹ 1.24 L
MODE
Full timeDURATION
24 MonthsMaster of Engineering (ME) in VLSI Design is a two-year full-time postgraduate program recognized by AICTE and offered by the Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal.
| Exams and Events | Dates |
|---|
GATE Answer Key Date - Final answer key (Mode - Online) | 22 Aug'26 - 18 Sep'26 |
GATE Score Card Date (Mode - Online) | 26 Sep'26 - 26 Sep'26 |
GATE Result Date (Mode - Online) | 18 Oct'26 - 18 Oct'26 |
A candidate seeking admission to M.E./M.Tech. courses should be a Graduate in Engg./Technology with at least 50% marks in aggregate, Candidate belonging to SC, ST, OBC(Excluding Creamy Layer) category of Madhya Pradesh with at least 45% marks in aggregate. Bachelors degree be of minimum of four years duration should have been obtained from any AICTE approved institution or Indian University or from a foreign University recognised by AIU or any Institutes of national importance (i.e. IITs/IISc/ NITs etc.), duly recognized by the MHRD, as equivalent thereto.
Through GATE entrance.